`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   14:10:23 11/22/2013
// Design Name:   Level_Decoder
// Module Name:   G:/Xilinx_Proj/H_264_test/Level_decodertest.v
// Project Name:  H_264_test
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: Level_Decoder
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module Level_decodertest;

	// Inputs
	reg [63:0] Code;
	reg [4:0] TotalCoeff;
	reg [1:0] Tls;
	reg Clk;
	reg Rst;
	reg Sig_start;

	// Outputs
	wire Sig_done;
	wire [7:0] Level_code_length;
	wire [3:0] Level_cnt;
	wire [8:0] Level_0;
	wire [8:0] Level_1;
	wire [8:0] Level_2;
	wire [8:0] Level_3;
	wire [8:0] Level_4;
	wire [8:0] Level_5;
	wire [8:0] Level_6;
	wire [8:0] Level_7;
	wire [8:0] Level_8;
	wire [8:0] Level_9;
	wire [8:0] Level_10;
	wire [8:0] Level_11;
	wire [8:0] Level_12;
	wire [8:0] Level_13;
	wire [8:0] Level_14;
	wire [8:0] Level_15;
	wire [63:0] Code_t;
    reg [8:0] Level_0_in;
    reg [8:0] Level_1_in;
    reg [8:0] Level_2_in;
	reg [4:0] cnt;
	wire [3:0] tLevel_prefix;
	wire [15:0] tLevel_suffix;
	wire [3:0] tLevelSuffixsSize;
	// Instantiate the Unit Under Test (UUT)
	level_decoder uut (
		.Code(Code), 
		.TotalCoeff(TotalCoeff), 
		.Tls(Tls), 
		.Clk(Clk), 
		.Rst(Rst), 
		.Sig_start(Sig_start), 
		.Sig_done(Sig_done), 
		.Level_code_length(Level_code_length), 
		.Level_cnt(Level_cnt), 
        .Level_0_in(Level_0_in),
        .Level_1_in(Level_1_in),
        .Level_2_in(Level_2_in),
		.Level_0(Level_0), 
		.Level_1(Level_1), 
		.Level_2(Level_2), 
		.Level_3(Level_3), 
		.Level_4(Level_4), 
		.Level_5(Level_5), 
		.Level_6(Level_6), 
		.Level_7(Level_7), 
		.Level_8(Level_8), 
		.Level_9(Level_9), 
		.Level_10(Level_10), 
		.Level_11(Level_11), 
		.Level_12(Level_12), 
		.Level_13(Level_13), 
		.Level_14(Level_14), 
		.Level_15(Level_15)
	);

	initial begin
		// Initialize Inputs
		Code = 0;
		TotalCoeff = 0;
		Tls = 0;
		Clk = 0;
		Rst = 1;
		Sig_start = 0;

		// Wait 100 ns for global reset to finish
		#100;
      cnt = 0;  
		// Add stimulus here
		#50 Rst = 0;
		#50 Rst = 1;
	end
	always #25 Clk=~Clk;
	always @(posedge Clk or negedge Rst) begin
		if(!Rst) begin
			cnt <= 0;
		end
		else begin
			case(cnt)
			0,1,2,3,4,5,6,7,8,9:begin
				cnt<=cnt+1;
			end
			10:begin
				Code <=16'b1110100001001000 ;TotalCoeff<=5 ; Tls<=1 ;Sig_start<=1;cnt<=cnt+1;
                Level_0_in <= -1;Level_0_in<=0;Level_0_in<=0;
			end	
			11:begin
				Sig_start<=0;
				if(Sig_done==1'b1)
					cnt<=cnt+1;
				else
					cnt<=cnt;
			end	
			12:begin
				Code <=16'b0100100 ;TotalCoeff<=5 ; Tls<=2 ;Sig_start<=1;cnt<=cnt+1;
                Level_0_in <= -1;Level_0_in<=-1;Level_0_in<=0;
			end	
			13:begin
				Sig_start<=0;
				if(Sig_done==1'b1)
					cnt<=cnt+1;
				else
					cnt<=cnt;
			end
			14:begin
				Code <=16'b01001 ;TotalCoeff<=5 ; Tls<=3 ;Sig_start<=1;cnt<=cnt+1;
                Level_0_in <= -1;Level_0_in<=0;Level_0_in<=0;
			end	
			15:begin
				Sig_start<=0;
				if(Sig_done==1'b1)
					cnt<=cnt+1;
				else
					cnt<=cnt;
			end
			16:begin
				cnt<=cnt;
			end
			endcase
		end
	end
   
endmodule

